VIT was established in the year 1984 as Vellore Engineering College by Dr.G.Viswanathan, Founder & Chancellor. The institute was upgraded as a university in recognition of its academic excellence in 2001 by the Ministry of Human Resources Development, Government of India. VIT today comprises of twelve constituent schools and interdisciplinary centers offering 24 undergraduate, 30 postgraduate and research programs up to Ph.D. level. With the aim of providing quality higher education at par with international standards, VIT persistently seeks and adopts innovative methods in teaching and learning. The university has students from all corners of the globe, nurtured by learned and experienced faculty. VIT has signed Memoranda of Understanding for the exchange of students and faculty, research collaborations and consultancy activities with various international universities, research organisations and industries. VIT University is the first Indian institute to get international accreditation from IET, UK, and NAAC, India. All B.Tech programmes at VIT are accredited by the Engineering Accreditation Commission of ABET, USA. VIT is also ranked as No.1 private engineering institute by MHRD (NIRF-2016 ranking).
The 2nd International Conference on Microelectronics Devices, Circuits and Systems (ICMDCS 2020) will be held at the Vellore Institute of Technology (VIT), Vellore India from 22nd to 24th January 2020. ICMDCS 2020 will be organized by Department of Micro and Nanoelectronics and technically co-sponsored by IEEE Bangalore Section, CAS Chapter. The conference covers the subject areas including: digital IC design, analog/RF/Mixed Signal IC design, Device Modeling and Technology, RF communication circuits, embedded systems; nonlinear circuits and system In addition to the technical papers, the conference also covers tutorials on recent advancements in the above said areas, Keynote and Plenary sessions by leading industry leaders and renowned academicians.
Call for Papers
Digital Design (Track-1)
Logic and physical synthesis, physical design, timing and signal integrity, power integrity, design for manufacturability, design for yield, design challenges for advanced technology nodes, low-power design, power-aware and energy-efficient design, thermal management, battery-aware design, energy harvesting, CAD Tools, Verification methodologies, DFT, fault modeling and simulation, ATPG, BIST, board-level and system-level test, memory test.
Analog, Mixed- Signal and RF Design: (Track-2)
Design of analog, mixed-signal, and RF IP, high-speed wired and wireless communication interfaces, low-power analog and RF, memory design, standard cell design.
Technology and Devices: (Track-3)
Advanced Logic and Memory devices, Flexible and Organic Electronics, Photovoltaics and Energy Systems, Nano-electro-mechanical Systems and Sensors, Optoelectronics and Photonics, Compound Semiconductor Devices, Computational Modeling at the Nanoscale, Semiconductor Materials and Processes, Emerging Materials and Devices, Device Reliability.
System-level Design: (Track-4)
System-level design methodologies, processor and memory design, multicore systems, GPU design, on-chip communication architectures and networks-on-chip, performance analysis, defect-tolerant architectures, machine learning), : Hardware/Software co-design, embedded SoC, embedded multi-core systems, board-level hardware, hardware platforms for Internet-of-Things (IoT) devices, Reconfigurable computing, FPGA architecture and FPGA circuit design, CAD for FPGA, FPGA prototyping, FPGA-based accelerators for cloud servers, Wireless sensor networks, low-power wireless systems, wireless protocols, wireless power delivery.
Emerging Technologies: (Track-5)
MEMS, CMOS sensors, design methodologies for nanotechnology, post-CMOS devices, biomedical circuits, carbon nanotube-based computing, spintronics, silicon photonics, neuromorphic computing.
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- Should you have any questions, please feel free to contact us.
English is the official language of the conference; the paper should be written and presented only in English.
Presentation & Publication (Full paper)
Full paper is requested, if you are also considering publishing your paper.
Articles submitted to the conference should report original, previously unpublished research results, experimental or theoretical and must not be under consideration for publication elsewhere. We firmly believe that ethical conduct is the most essential virtue of any academic. Any act of plagiarism is unacceptable academic misconduct and cannot be tolerated. If an author is found to commit an act of plagiarism, the following acts of sanction will be taken:
- Reject the article submitted or delete the article from the final publications.
- Report the authors violation to his/her supervisor(s) and affiliated institution(s).
- Report the authors violation to the appropriate overseeing office of academic ethics and research funding agency.
- Reserve the right to publish the authors name(s), the title of the article, the name(s) of the affiliated institution and the details of misconduct, etc. of the plagiarist”.
Formatting & Paper Length Limitation
Please follow the instructions of the IEEE Template when editing paper. For accepted papers, one registration covers 5 pages including tables, figures and references, and additional pages will be chargeable.
Please make a note!
Full paper submission
Notification of acceptance
Final paper submission
Registration (Early Bird)
Registration(Conference & Tutorial)
Check our gallery from the ICMDCS – 2017
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- Academician (IEEE Member)*
- Academician (Non-IEEE Member)*
- Industry Delegates
- Foreign Delegates
- USD 300
- Academician (IEEE Member)
- Academician (Non-IEEE Member)
- Industry Delegates
- Foreign Delegates
- USD 50
*First Author with Multiple Submission is eligible for reduced registration fee for the only one
*If more than one author of an accepted paper wishes to attend the conference, all such authors need to register separately as an author.